Yufan Du — PhD Student, UCLA Computer Science

01About

I am a first-year PhD student in Computer Science at UCLA, advised by Prof. Jason Cong in the VAST lab. I work on the layer where hardware and software meet: domain-specific accelerators, the compilers that target them, and the systems that serve large language models.

Before UCLA, I studied applied physics and computer science at Peking University, where I worked on differentiable optimization for chip physical design — teaching gradient descent to place and size logic gates. I also spent a summer at UT Austin with Prof. David Z. Pan's group working on gate sizing.

Interests: Domain-specific accelerators · Compilers · LLM serving systems · ML for systems

2025 –PhD in Computer Science · University of California, Los Angeles
2021 – 2025BSc in Computer Science · Peking University
2021 – 2025BSc in Applied Physics · Peking University

applied physicschip physical designcompilers & architectureLLM serving systems

02News

Jun 2026Our DAC 2026 paper on quad-gradient gate sizing was nominated for Best Paper.
Jun 2026Started as an Applied Scientist Intern at AWS in San Jose, working on multi-node, multi-GPU LLM serving.
Sep 2025Joined UCLA VAST lab as a PhD student.
May 2025Our ISEDA 2025 paper on differentiable gate sizing received an Honorable Mention Paper Award.
Oct 2024Our ICCAD 2024 paper on fusing global placement and gate sizing was nominated for Best Paper.
Oct 2024Our team won first place (out of 45 teams worldwide) in ICCAD 2024 Contest Problem C — scalable gate sizing with ML and GPU acceleration.

03Publications

2026

Disentangled Differentiable Timing-Power Co-Optimization with Quad-Gradient Gate Sizing

Zixuan Pan*, Zizheng Guo*, Yufan Du, Runsheng Wang, Yibo Lin

DAC 2026physical designBest Paper Nominee

LOT YFD-26A·DAC — teaching timing and power to stop fighting over the same gates

2025

Differentiable Physical Optimization

Yufan Du, Zizheng Guo, Runsheng Wang, Yibo Lin

ICCAD 2025physical designpdf

LOT YFD-25B·ICCAD — the thesis statement: chip physical design as one differentiable program

Addressing Continuity and Expressivity Limitations in Differentiable Physical Optimization: A Case Study in Gate Sizing

Yufan Du, Zizheng Guo, Yang Hsu, Zhili Xiong, Seunggeun Kim, David Z. Pan, Runsheng Wang, Yibo Lin

ISEDA 2025physical designHonorable Mention Paper Awardpdf

LOT YFD-25C·ISEDA — where gradient descent trips on discrete gates — and how we smoothed the floor

2024

PowPrediCT: Cross-Stage Power Prediction with Circuit-Transformation-Aware Learning

Yufan Du, Zizheng Guo, Xun Jiang, Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Runsheng Wang, Ru Huang

DAC 2024ML × EDApdf

LOT YFD-24D·DAC — predicting post-layout power before the layout exists

Fusion of Global Placement and Gate Sizing with Differentiable Optimization

Yufan Du, Zizheng Guo, Yibo Lin, Runsheng Wang, Ru Huang

ICCAD 2024physical designBest Paper Nomineepdf

LOT YFD-24E·ICCAD — placement and sizing were always optimized as strangers; we fused them

HeteroExcept: A CPU-GPU Heterogeneous Algorithm to Accelerate Exception-aware Static Timing Analysis

Zizheng Guo, Zuodong Zhang, Wuxi Li, Tsung-Wei Huang, Xizhe Shi, Yufan Du, Yibo Lin, Runsheng Wang, Ru Huang

ICCAD 2024CPU–GPU systemspdf

LOT YFD-24F·ICCAD — timing exceptions look hopelessly sequential — until you split them across CPU and GPU

* equal contribution

04Experience

Jun 2026 – now
Applied Scientist Intern · Amazon Web Services, San Jose, CA
Multi-node, multi-GPU LLM serving optimization.
Jun 2024 – Sep 2024
Undergraduate Research Intern · UT Austin, Austin, TX
Differentiable algorithms for chip physical design, with Prof. David Z. Pan's group.

05Selected Projects

ICCAD 2024 CAD Contest, Problem C — First Place — Scalable logic gate sizing with ML techniques and GPU acceleration; our solution ranked first among 45 teams worldwide.
GPU-accelerated gate-level circuit simulation — CUDA kernels exploiting low switching activity to accelerate gate-level simulation of large VLSI designs.
SysY → RISC-V compiler — A complete compiler from SysY (a C subset) to RISC-V assembly: lexing, parsing, IR, optimization passes, codegen.
FPGA snake game with computer vision — Classic snake plus a CV-based 3D human-computer interface, squeezed onto a resource-limited FPGA.